SimGen 2.95

SimGen is an EDIF/VHDL/FPGA to ASIC Conversion Utility and Simulation Generator for Tanner Tools EDA.
  - saves thousands of dollars when converting an FPGA to an ASIC
  - enables VHDL simulation based on final chip layout
  - improves routine operations (specifying pads/pin outs, setting up GateSim and Spice runs, etc.)

Features include:

1. Generates (extracts) VHDL files from chip layout to support verification in VHDL design flows

• cell-based block extractor
• complete fanout report
• supports VHDL or GateSim simulation from extracted netlist

2. Automatically generates simulation files (.sim & .vec) for GateSim

• sets up template files with port I/O lists
• restores true port names (replacing meaningless parameters)

3. Supports import of VHDL/EDIF into the complete Tanner environment (GateSim, SEdit, LEdit, LVS) by way of Nettran using .mac files

• new in 2.9 - inverter optimization on preset/clear lines which must be inverted
• new in 2.9 - fully supports OrCAD R9/Exemplar synthesizer
• new in 2.95 - fanout management capability
• supports Altera Max 3 and OrCAD R7.2 synthesizers
• sample project included

4. Cleans up and repairs netlists (mac, tpr and spice files) so they work as expected when going from one tool to another

• new in 2.9 - provides for PAD/Pin out definitions in an external file (rather than schematic or VHDL)
• fixes layout-extracted spice files to be actually compatible with TSpice
• fixes tpr files to preserve top level node (I/O port) names

5. Provides a Windows control shell

• launches and generates commands and setup files for GateSim & Nettran
• quick launch of file editing and wave viewing functions
• superior to the limited shell program provided by Tanner

---> soon to come: automatic "standard block" construction to support hierarchical auto-routing!

Includes 4 complete examples of VHDL/FPGA conversions with cell library mapping and full verification:
  1 - Xilinx XC4000 design done in VHDL using OrCAD Express 7.2
  2 - Altera 7000 design done in VHDL using MAX-3
  3 - Altera 7000 design done in VHDL using OrCAD Express 7.2
  4 - Generic design done in VHDL using OrCAD Express R9/Exemplar

          
                 SimGen 2.8 w/OrCad7.2               SimGen2.9 w/OrCadR9-Exemplar      
          sample difference in ASIC core sizes for 4-bit counter sample project

ASIC Conversion & Verification Illustration:

your VHDL design...	ASIC layout core	VHDL extracted from layout for verification
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity count is   port(clkin: in std_logic;   reset: in std_logic;   value: out std_logic_vector(3 downto 0)); end count; architecture count_a of count is   signal previous : std_logic_vector(3 downto 0); begin   process (previous,clkin,reset) begin     if (reset='1') then     previous<="0000";   else     if (clkin'event and clkin='1') then       previous<=std_logic_vector         (resize(unsigned(previous),4) + 1);     end if;   end if;   value<=previous;   end process; end count_a;		library IEEE; -- $written by blk_xtrk.c - top=count use IEEE.STD_LOGIC_1164.all; entity count is port ( clkin : in std_logic ; reset : in std_logic ; value : out std_logic_vector ( 3 downto 0 ) ); end count; architecture count_1 of count is signal vdd: std_logic; signal gnd: std_logic; signal exp_n136 : std_logic; signal exp_n213 : std_logic; . . . (more) begin vdd<='1'; gnd<='0'; Ii1 : buf1 port map (exp_n136,value(2)); Ii2 : nand2c port map(exp_n213,exp_n201,ncx1,exp_n210); Ii3 : inv port map (exp_n201,exp_n212); Ii4 : inv port map (exp_n135,exp_n213); . . . (more)

Use the same test bench before & after routing and compare results!

Super easy pad/pin setup... <1 PADOUT PAD_R2 VALUE2 <2 PADOUT PAD_T1 VALUE3 <3 PADIN  PAD_L1 RESET <4 PADIN  PAD_L2 CLKIN <5 PADOUT PAD_B1 VALUE0 <6 PADOUT PAD_B2 VALUE1

You can download a 30-day evaluation copy.  This is a short .zip file.  Unzip to a temporary directory and run install.exe.  It is designed for you to keep all your project files in a project directory, and manages the NetTran interface to make this happen.  Win'95 is the preferred target OS.  SimGen is not listed on the order page.  Contact MediaComm to order a registered copy.  

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